摘要
针对已有锁相电路的特性不能完全满足实际项目需求的缺点,设计了一种新的2.5GHz锁相环检测电路。完成了锁定检测电路的整体设计,并基于SMIC 0.18μm工艺进行重新设计。采用HSPICE进行仿真,结果表明,检测精度得到提高。
Traditional PLL cannot accomplish lock detection with increasing clock frequency. A new PLL detection technique was presented. A lock detection circuit was designed in a top-down way, and reverse extraction was made. With extracted circuit, the lock detection circuit was redesigned based on SMIC 0. 18 μm process. HSPICE simulation results showed that detection accuracy of the circuit was improved.
出处
《微电子学》
CAS
CSCD
北大核心
2012年第4期493-496,共4页
Microelectronics
关键词
锁相环
锁定检测
反向提取
Phase-locked loop
Lock detection
Reverse extraction
