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可重构路由器报文转发引擎设计与实现 被引量:1

Design and implementation of packet forwarding engine for reconfigurable routers
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摘要 网络处理功能的时空演化特性要求可重构路由器报文转发引擎除具有基本报文分组交换能力外,还应具有可重构能力。针对上述需求,构建了面向可重构路由器的报文转发引擎构件重构模型,并基于Pass-Through模式设计实现了可重构FPGA器件与网络处理器相结合的程序/电路构件运行环境。系统实现与应用测试结果表明,可重构路由器报文转发引擎在保证高吞吐率、低延迟的报文转发处理性能的同时,可有效支撑多样化业务构件灵活重构与映射。 The packet forwarding engine should provide not only the basic packet switching function, but also the reconfigurable ability for supporting the network processing functions evolving with time and space. Aiming at the above requirements, a component reconfiguration model of packet forwarding engine for the reconfigurable routers was proposed, and the program/circuit component running environment consisting of FPGA and network processers was designed and implemented based on the Pass-Through mode. The system implementation and application experimental results show that the packet forwarding engine for reconfigurable routers can support flexibly reconfiguration and mapping for the diverse service components, and it can provide high throughput and low-latency packet forwarding ability.
出处 《通信学报》 EI CSCD 北大核心 2012年第8期42-51,共10页 Journal on Communications
基金 国家重点基础研究发展计划("973"计划)基金资助项目(2009CB320503) 国家高技术研究发展计划("863"计划)基金资助项目(2008AA01A323 2008AA01A325 2009AA01A334)~~
关键词 路由器 转发引擎 可重构 构件 router forwarding engine reconfiguration component
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参考文献19

  • 1李玉峰,邱菡,兰巨龙.可重构路由器研究的现状与展望[J].中国工程科学,2008,10(7):82-89. 被引量:8
  • 2HU C C, WU C, X W, et al. On the design of green reconfigurable router toward energy efficient internet[J]. IEEE Communications Magazine, 2011, 49(6):83-87.
  • 3龚正虎,傅彬,卢泽新.软件集群路由器体系结构研究[J].国防科学技术大学学报,2006,28(3):40.43.
  • 4LEE D C, MIDKIFF S F. Reconfigurable routers: a new paradigm for switching device architecture[EB/OL], http://www.ccm.ece.vt.edu/ papers/, 1998.
  • 5KOHLER E, MORRIS R, CHEN B, et al. The click modular router[A]. Proceedings of the ACM Symposium on Operating Systems Principles (SOSP)[C]. 1999.217-231.
  • 6DAN D, ZUBIN D, GURU P, et al. Router plugins: a software archi- tecture for next generation routers[A]. Proc of ACM SIGCOMM[C]. 1998.229-240.
  • 7HAN S, JANG K, PARK K, et al. Packet shader: a GPU-accelerated software router[A]. ACM SIGCOMM[C]. New Delhi, India, 2010. 195-206.
  • 8LEE D, HARPER S, ATHANAS P, et al. A stream-based reconfigur- able router prototype[A]. IEEE International Conference on Commu- nications[C]. Vancouver, BC, 1999. 581-585.
  • 9LOCKWOOD J, NAUFEL N, TURNER J, et al. Reprogrammable network packet processing on the field programmable port extender (FPX)[A]. ACM International Symposium on Field Programmable Gate Arrays (FPGA)[C]. Monterey, CA, USA, 2001.87-93.
  • 10NAOUS J, GIBB G, BOLOUKI S, et al. NetFPGA: reusable router architecture for experimental research[A]. Proceedings of the ACM Workshop on Programmable Routers for Extensible Services of To- morrow (PRESTO '08)[C]. New York, NY, USA, 2008. 1-7.

二级参考文献38

  • 1Duncan Buell, Tarek El-Ghazawi, Kris Gaj,et al. Guest Editors' Introduction: High-Performance Reconfigurable Computing [J]. Computer, 2007 (3):23-27.
  • 2Zachary K Baker, Viktor K Prasanna. An Architecture for Efficient Hardware Data Mining using Reconfigurabte Computing Systems [ C ]//14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. 2006:67 - 75.
  • 3Tahir M A, Bouridane A. A Fpga Based Coprocessor for Cancer Classification Using Nearest Neighbor Classifier [ C ]//2006 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2006 Proceedings. 2006 : 1012 - 1015.
  • 4Estrin G. Parallel Processing in a Restructurable Computer System [ J ]. IEEE Trans on Electronic Computers, 1963,12(5) :747 -755.
  • 5Kartashev S P, Kartashev S I. Dynamic Architectures: Problems and Solutions [ J ]. Computer, 1978,11 ( 7 ) : 26 -40.
  • 6Rose J, Gamal A El A. Sangiovanni-Vincentelli, Architecture of Field-Programmable Gate Arrays [ C ] //Proceedings of the IEEE. 1993, 81(7) : 1013 - 1029.
  • 7Butel P. Manaping Partial dynamic Reconfiguration in Virtes-Ⅱ Pro FPGAS [EB/OL]. (2004 - 07 - 01) [ 2008 - 09 -01 ]. http: www. xilinx, com/publications/ xeellonline/xcess-50/xc-pdf/xc-mbdaso, pdf.
  • 8ALIERA corporation. Stratix Ⅱ GX Device Hand book [ EB/OL]. (2007 - 10 - 01) [200S - 06 - 01 ]. http:// www. ahera, com. cn/literature/lit-s2gx, jsp.
  • 9Hadley J, Hutchings B. Design methodologies for partially reconfigured systems [ C ]//IEEE Workshop on FPGAs for Custom Computing Machines. 1995:78 -84.
  • 10Amerson R, Carter R J, Culbertson W B, et al. Teramac re-configurable custom computing [ C ]//Proceedings of the 1995 IEEE Symposium on FPGA' s for Custom Computing Machines. Napa: CA, 1995:32-38.

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