基于DSP Builder的数字滤波器设计与实现

DSP builder-based digital filter design and implementation

现场可编程门阵列(FPGA)器件广泛用于数字信号处理领域,而使用VHDL或VerilogHDL语言进行设计比较复杂。提出一种采用FDATOOL工具和DSP Builder实现FIR滤波器的设计方案,按照MATLAB/Simulink/DSP Builder/QuartusII设计流程,使用FDATOOL工具可以实时调整滤波器的参数,采用DSP Builder设计了一个16阶FIR低通滤波器模型,并完成了仿真与验证,将模型转换生成VHDL代码,实现了基于FPGA的数字滤波器的设计。结果表明,该方法简单易行,易修改与移植,可满足设计要求,它验证了采用DSP Builder实现数字滤波器设计的独特优势。

Field programmable gate array（FPGA） devices are widely used in digital signal processing applications,the use of VHDL or VerilogHDL languages to design more complex.Proposed a FDATOOL tool and DSP Builder FIR filter design program of MATLAB/Simulink/DSP Builder/the Quartus II design flow use the FDATOOL tools to adjust the filter parameters in real time using DSP Builder design a 16-order FIRlow-pass filter model,and complete the simulation and verification,model transformation to generate the VHDL code,and FPGA-based digital filter design.The results show that the method is simple,easy to modify and transplantation,can meet the design requirements,it verifies that the unique advantages of the digital filter design using DSP Builder.