乘法器模块在FPGA中的实现

The Realization of Multiplier Module in FPGA

作为数字信号处理领域的基本运算单元,乘法器在其中起到了至关重要的作用。本文设计了三种基于FP-GA的数字乘法器模块,包括传统乘法器,LUT乘法器和Booth算法的乘法器,利用Modelsim仿真软件分别对三种算法进行了仿真,并用QuartusII软件对所编写的Verilog程序进行编译综合,这里用到的FPGA芯片是Altera公司生产的cycloneII器件,最后对结果进行了说明。

As the basic computing unit in digital signal processing area, multiplier plays a crucial role. This paper designs three digital multiplier modules based on FPGA, including traditional multiplier, LUT multiplier and Booth algorithm multiplier. With Modelsim simulation software, the three algorithms are simulated, and the written Verilog program is compiled with QuartusⅡ software, here the FPGA chip used is the cycloneⅡ device produced by Altera Company, finally the results are illustrated.