应用于射频收发机的低功耗频率综合器

Low Power Frequency Synthesizer for RF Transceiver

基于0.18μm 1P6M CMOS工艺,设计并实现了一种用于工作在2.4 GHz ISM频段的射频收发机的整数型频率综合器。频率综合器采用锁相环结构,包括片上全集成的电感电容压控振荡器、正交高频分频器、数字可编程分频器、鉴频鉴相器、电荷泵、二阶环路滤波器,为接收机提供正交本地振荡信号并驱动功率放大器。通过在PCB板上绑定裸片的方法进行测试,测试结果表明,压控振荡器的频率覆盖范围为2.338～2.495 GHz;锁定频率为2.424 GHz时,频偏3 MHz处的相位噪声为-113.4 dBc/Hz,带内相位噪声为-65.9 dBc/Hz;1 MHz处的参考杂散为-45.4 dBc,满足收发机整体性能指标的要求。在1.8 V电源电压下,频率综合器整体消耗电流仅为6.98 mA。芯片总面积为0.69 mm×0.56 mm。

Based on 0.18 μm 1P6M CMOS technology,an integer-N frequency synthesizer for a radio frequency transceiver of 2.4 GHz ISM application was implemented.The frequency synthesizer is based on a phase locked loop which incorporates integrating the LC-voltage controlled oscillator,I/Q high frequency divider,programmable frequency divider,phase frequency detector,charge pump and 2-order loop filter into a single chip.It provides I/Q located oscillator for the receiver and drives the power amplifier.Measurements were performed on chips mounted on PCBs,and the test shows that the system requirements are met.The VCO covers the frequency of 2.338-2.495 GHz.At 2.424 GHz,the measured phase noise at 3 MHz offset and in-band are-113.4 dBc/Hz and-65.9 dBc/Hz,relatively,and the reference spur is-45.4 dBc at 1 MHz.The frequency synthesizer consumes a total current of 6.98 mA from a 1.8 V power supply.The chip size is 0.69 mm×0.56 mm.