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基于快速模拟退火算法的可切割布图规划方法 被引量：2

Slicing Floorplanning Based on Fast Simulated Annealing
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摘要 为了提高基于经典模拟退火算法的可切割布图规划方法的效率和效果,提出了一种动态改变温度下降比例来实现快速模拟退火算法的可切割布图规划方法,并将提出的方法应用于MCNC基准电路进行测试.实验结果表明该算法可以提高搜索优化解的效率和效果. In order to improve the efficiency and effectiveness of slicing floorplanning based on classical simulated annealing. A new slicing floorplanning based on fast simulated annealing which can change the ratio of temperature descending dynamically are proposed. The proposed method is applied to MCNC benchmark circuits, and the experimental results show that this algorithm can improve the efficiency and effectiveness of searching optimization solution.
作者 罗佐 杜世民 戚利侠 夏银水
机构地区 宁波大学电路与系统研究所
出处 《微电子学与计算机》 CSCD 北大核心 2012年第9期109-112,共4页 Microelectronics & Computer
基金 国家自然科学基金重点项目(61131001) 浙江省自然科学基金重点项目(Z1090622) 教育部博士点基金(20113305110001)
关键词 VLSI设计 可切割布图规划 快速模拟退火算法 波兰正则表达式 VLSI desigm slicing floorplanning fast simulated annealing normalized polish expression
分类号 TP391 [自动化与计算机技术—计算机应用技术]
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参考文献8

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同被引文献18

  • 1陈华根,李丽华,许惠平,陈冰.改进的非常快速模拟退火算法[J].同济大学学报（自然科学版）,2006,34(8):1121-1125. 被引量：46
  • 2郝冬艳,张明,郑伟.低功耗VLSI芯片的设计方法[J].微电子学与计算机,2007,24(6):137-139. 被引量：15
  • 3周顺先,林亚平,王耀南,易叶青.基于二阶隐马尔可夫模型的文本信息抽取[J].电子学报,2007,35(11):2226-2231. 被引量：25
  • 4Frietag D, Mc Callum A. Information extraction with HMMs and shrinkage[C]//Proceedings of the AAAI' 99 Workshop on Machine Learning for Information Ex- traction. Orlando, 1999, 31-36.
  • 5Frietag D, McCallum A. Information extraction struc- tures learned by stochastic optimization[C]//Proceed- ings of the Eighteenth Conference on Artificial Intelli- gence. Berlin, 2000 : 584-589.
  • 6Yan J Z, Viswanathan N, Chu C. An effective floor- plan-guided placement algorithm for large-scale mixed- size designs[J]. ACM Transactions on Design Auto- mation of Electronic Systems, 2014, 19(3) :1-25.
  • 7WuGM, WuSW, ChangYW, etal. B*-Trees: a new representation for non-slicing floorplans [C]// Proc of ACM/IEEE Design Automation Conference. LOS Angeles, California, USA. IEEE, 2000 : 458-463.
  • 8Murata H, Fujiyoshi K, Nakatake S, et al. VLSI rood-ule placement based on rectangle-packing by the se- quence-pair[J]. IEEE Transactions on Computer-Ai- ded Design of Integrated Circuits and Systems, 1997, 15(12) : 1518-1524.
  • 9Young E F Y, Chu C CN, Ho M L. Placement con- straints in floorplan design[J]. IEEE Transactions on Very Large Scale Integration Systems, 2004, 12(7): 735 - 745.
  • 10Ma Y, Hong X, Dong S, et al. Floorplanning with a- butment constraints based on corner block list[J].In- tegration the VLSI Journal, 2001, 31(1) :65-77.

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微电子学与计算机
2012年 第9期

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