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双环网络G(N;1,s)的L形瓦仿真算法改进 被引量:1

Improved Algorithm to Simulate L-shaped Tile of Double-loop NetworksG(N;1,s)
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摘要 利用仿真来研究双环网络L形瓦,在国内外文献中尚不多见,文献[1]提出了一种仿真算法,文献[2]使用数组对文献[1]的算法作了改进.其不足之处是使用了过多过长的中间数组,影响了仿真速度.针对这一不足,根据L形瓦的h边特性,使用了更少更短的数组改进了文献[2]的算法,实验结果表明,改进的算法极大地提高了仿真速度.此外还给出了L形瓦的h边分布特点,并作了进一步分析. There are few reports which using simulation to research doubl e-loop networks. Reference [ 1 ] presented a simulation algo- rithm, and reference [ 2 ] presented an improved algorithm with array, But the disadvantage of this algorithm is using too much and too long middle array, so it spends too much time to calculate. Therefore, an improved algorithm with too little and too short array by the characteristic of L-shape tile's h-edge, The result of experiments indicated that the improved algorithm improved the speed of cal- culation more. Furthermore, the distributing figure of L-shaped tile's h-edge is put forward, and analysis its character.
出处 《小型微型计算机系统》 CSCD 北大核心 2012年第9期2053-2055,共3页 Journal of Chinese Computer Systems
基金 国家青年自然科学基金项目(61003311)资助 安徽省高校自然科学基金项目(KJ2010A051)资助
关键词 双环网络 仿真 紧优 L形瓦 double-loop networks simulate tight optimal L-shaped tile
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  • 1陈协彬.步长有限制的双环网络的最优路由算法[J].计算机学报,2004,27(5):596-603. 被引量:34
  • 2方木云,赵保华,屈玉贵.基于圈的紧优双环网络G(N;1,s)求解算法[J].华中科技大学学报(自然科学版),2005,33(6):17-19. 被引量:6
  • 3方木云,赵保华,屈玉贵.非单位步长双环网络G(N;r,s)的L形瓦仿真算法[J].系统仿真学报,2006,18(10):2963-2965. 被引量:6
  • 4方木云,赵保华.新的无向双环网络G(N;±1,±s)直径求解方法[J].通信学报,2007,28(2):124-129. 被引量:19
  • 5Chen C ~, Hwang F K. Equivalent L-shapes of double-loop networks for the degenerate case [ J ]. Journal of Interconnec- tion Networks,2000,1 ( 1 ) :47-60.
  • 6Hwang F K. A survey on multi-loop networks[ J]. Theoretical Computer Science ,2003,299 ( 1 ) : 107-121.
  • 7Wong C K, Coppersmith D. A combinatorial problem related to multi - module memory organizations [J].Journal of ACM, 1974,21 ( 3 ) :392-402.
  • 8Koibuch M, Matsutani H, Amano H, et al. A case for random shortcut topologies for HPC interconnects [ C]//Proc of 39th annual international symposium on computer architecture. [ s. L ] :IEEE,2012:177-188.
  • 9Kim J, Balfour J, Dally W. Flattened butterfly topology for on- chip networks [ C ]//Proceedings of the 40th annual IEEE/ ACM international symposium on micro-architecaLre. [ s. L ] : IEEE Computer Society ,2007 : 172-182.
  • 10Fujiwara I, Koibuchi M, Casanova H. Cabinet layout optimiza- tion of supercomputer topologies for shorter cable length [C]//Proc of 13th international conference on parallel and distributed computing, applications and technologies. [ s. 1. ] : IEEE ,2012:227-232.

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