一种基于DPA的高速数据流接收的校正方法

Correction method of high-speed data stream receiving based on DPA

在高速数据采集系统中,对于高速数据流的接收的可靠性,是整个系统正常工作的前提与保证。在基于FPGA+DSP架构的高速数据采集系统中,由于FPGA布局布线、环境温度、工作电压的变化等各方面的影响,可能造成数据同步时钟与数据对应关系的偏移,由此而可能造成高速数据流接收的不可靠。针对以上问题,基于DPA(dynamic phase alignment,动态相位调整)的设计思想,提出一种高速数据流接收的校正方法,并在FPGA+DSP架构的高速数据采集系统上设计实现,使得数据同步时钟的时钟沿与数据的有效窗口的最佳采样位置动态对齐。最终实验得到的数据和现象证明了该校正方法的可行性和稳定性。

The premise and guarantee of the effective functioning of a high speed acquisition system lie in the accuracy of high-speed data stream receiving. The influence of each element such as the variation of placement and routing of FPGA, ambient temperature and operating voltage may cause the offset of the correspondence between data synchronization clock and data, making the unreliability of high-speed data stream receiving in the high-speed data acquisition system based on FPGA＋ DSP. To solve these problems, a correction method based of the design idea of dynamic phase alignment is proposed and implemented in the high-speed data acquisition system based on FPGA＋DSP, making the edge of data synchronous clock dynamically alignment with the best sampling location of the data valid window. The data and statistics accumulated from experiments approved the feasibility and stability of the correction method.