一种高电源抑制比的LDO电路设计

Design of a Low-dropout Regulator with High Power Supply Rejection Ratio

设计一种基于0.35μm 2P4M CMOS工艺,具有高电源抑制比、快速负载瞬态响应特性的低压差线性稳压器电路。该电路通过采用缓冲运放来驱动LDO电路的功率调整管,有效提高了LDO电路的电源抑制比和负载瞬态响应特性。该电路的输入电压为3.3V-4V,输出电压为2.8V;负载电流范围为0.5mA到100mA,当负载电流在全负载范围内瞬变时,输出端过冲电压小于1mV;在全负载范围内,低频时,电路的电源抑制比达到-89dB以上,在1MHz时,电路的电源抑制比达到-60dB以上。

In this paper, a Low-Dropout Regulator with high power supply rejection ratio and fast response which is implemented in a standard 0.35gin 2P4M CMOS technology is proposed. The proposed LDO circuits achieve high pow- er supply rejection ratio and fast load transient response according to the impedance-attenuated buffer for driving the PMOS pass device. The input voltage varies from 3.3V to 4V, the output voltage is 2.8V, the load current transienl varies from 0.5mA to 100mA, the maximum overshoot voltage is less than lmV during the full load current transient. It reaches -89dB power supply rejection ratio at low flequeucy and about -60dB at 1MHz.