期刊文献+

数字信道化的级联设计 被引量:1

Design of Serial Digital Channelization
原文传递
导出
摘要 在宽带信号侦察中数字信道化是一个极其重要的环节。当侦察的信号带宽非常宽,需要的数字信道化个数很大时,用一级信道化实现非常困难。其中,大点数、高速率的DFT设计和硬件实现是一个最突出的难点。针对这个问题,提出了一种数字信道化的级联实现结构,把实信号的数字信道化与复信号的数字信道化级联起来,能够大大降低设计难度,并且这种基于模块化的设计便于工程实现。仿真结果证明,这种方法能够有效实现实信号的无盲区、抗混叠的频谱恢复。 Digital channelization plays a very important role in the detection of broad-band signal.When the signal band is very broad and the number of channel is rather large,it is quite difficult to realize the channelization through only one step.Among these,the design and hardware implementation of the large point-number and rapid DFT is the most prominent difficulty.Aiming at this problem,serial channelization architecture is proposed,which could make a serial connection between real signal digital channelization and complex signal digital channelization,thus to greatly reduce the design complexity.In addition,this design based on the module is very convenient to engineering implementation.Simulation result shows that the proposed method could efficiently accomplish the spectrum rebuilding without any blind zone and overlap.
出处 《通信技术》 2012年第9期43-45,49,共4页 Communications Technology
关键词 数字信道化 离散傅立叶变换 实信号数字信道化 复信号数字信道化 级联 digital channelization; DFT(Discrete Fourier Transform); real signal channelization; complex signal channelization; serial connection
  • 相关文献

参考文献8

二级参考文献22

  • 1付永庆,李裕.基于多相滤波器的信道化接收机及其应用研究[J].信号处理,2004,20(5):517-520. 被引量:44
  • 2路后兵,李永亮.一种高效的宽带数字信道化接收方法[J].无线电工程,2006,36(2):33-35. 被引量:8
  • 3董晖,姜秋喜,毕大平.多相滤波宽带信道化数字接收机[J].雷达科学与技术,2007,5(1):73-77. 被引量:17
  • 4郑继刚,安涛.宽带数字接收机信道化测频技术[J].舰船电子对抗,2007,30(3):59-62. 被引量:5
  • 5Fields T W, Sharpin D L, Tsui J B. Digital channelized IFM receiver[C]//IEEE Microwave Theory and Technology Symposium Digest ,1994, 3(5) : 1667 - 1670.
  • 6Zahirniak D R, Sharpin D L, Fields T W. A hardware-efficient, multirate, digital channelized receiver architecture[J].IEEE Trans. on Aerospace and Electronic Systems, 1998,34 (1) : 137 - 151.
  • 7Atmel C. AT84AD001B smart ADC datasheet[EB/OL].http:// www. e2v. com.2006.
  • 8Adhiwiyogo M. Virtex-4 high-speed dual data rate LVDS transceiver[EB/OL], http: // www.xilinx, com/support/documentation/application_notes/xapp705.pdf.2005 - 10 -8.
  • 9Sawyer N. 1:7 Deserialization in Spartan-3E/3A FPGAs at Speeds up to 666 Mbps[EB/OL]. http://www.xilinx, com/support/documentation/application notes/xapp485.pdf, 2006 -11 -10.
  • 10Xilinx C. Advanced ChipSync applications[EB/OL], http://www. xilinx. com/support/documentation/application_notes/xapp707, pdf, 2006 - 10 - 31.

共引文献24

同被引文献10

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部