高速CIC插值滤波器的位宽分析与优化

Analysis and Optimization of High-Speed CIC Interpolation Filter Width

分析了级联积分-梳状(CIC,Cascaded Integrator Comb)插值滤波器的位宽增长原因,重点研究了CIC插值滤波器非等值位宽的数据通路设计。在此基础上利用Matlab和Xilinx System Generator开发工具搭建了电路的系统模型,最后通过现场可编程门阵列(FPGA,Field Programmable Gate Array)完成电路的寄存器传输级(RTL,Register Transfer Level)验证,仿真结果表明电路设计具有很高的有效性和可行性。

This paper analyzes the increase of CIC （Cascaded Integrator Comb） interpolation filter width, and focuses on the data path design of non equivalent width. Based on this and with Matlab and Xilinx System Generator development tools, the system model of the circuit is built up, and finally through FPGA （Field Programmable Gate Array） RTL （Register Transfer Level）, the verification of the circuit is completed. And simulation indicates the effectiveness and feasibility of circuit design.