提高定点精度的FPGA信号处理算法

An Algorithm of Increasing Fixed-Point Accuracy for Signal Processing Systems with FPGA

为了满足速度、功耗等诸多限制的要求,数字信号处理算法常使用FPGA实现。而实现时由于硬件特点,通常将浮点运算转换成定点运算,但定点转换设计流程复杂、周期长,且存在数据范围和精度之间的矛盾。利用浮点数的优点,本文改进了基于FPGA的定点数的基本运算规则,有效解决了上述矛盾。本文详细论述了实现移位、加/减、乘、除基本运算模块的方法和步骤,最后以FIR数字滤波器为设计实例。仿真结果表明:改进的定点数算法比定点运算误差小、精度高、数据范围宽,能有效地防止溢出。

A digital signal processing system is usually implemented with Field Programmable Gate Arrays （FPGA） in order to be fast, low power, etc. The floating-point arithmetic must he translated to the fixed-point arithmetic which is used on FPGA currently. The process of a float-fixed conversion is complex, the period is long and the precision is proved to be low. Using the merit of floating-point arithmetic which can offer high precision and wide dynamic range, the paper puts forward an improved fixed point and basic arithmetic rule, details how to realize the following basic modules： shift bits, addition/ subtraction, multiplication and division. Finally, we take a digital filter, which is composed of basic modules, as an example. The simulation of the system shows that the improved fixed point format is higher in accuracy,wider in range than fixed-point computing, and it can effectively avoid overflow.