AES和SMS4密码算法的高效可重构实现

Implementation of efficient reconfigurability of AES and SMS4 encryption algorithm

可重构密码芯片提高了密码芯片的安全性和灵活性,具有良好的应用前景,但其处理速度较ASIC实现的专用密码芯片却有很大程度的下降。在此分析AES和SMS4密码算法的可重构性,利用流水线、并行处理和可重构技术,提出了一种可重构体系结构。基于该体系结构实现的AES和SMS4算法较其他同类设计相比,在资源规模相当的情况下,处理速度有了较大的提高。

The reconfigurable cipher chip, which can improve the security and flexibility of cipher chips, has good potential to become a vital component in the future. However, the speed of most reconfigurable cipher chips is pretty lower than that of ASIC chip. Based on the analysis about the structure of the AES and SMS4, a reconfigurable architecture is proposed in combination with pipeline, parallel processing and reconfiguration technology. The simulation results show that the pro- cessing speed of the AES and SMS4 algorithm implemented with the reconfigurable architecture is higher than other similar current algorithums when their resource scales are basically equal.