基于对称编码的综合测试压缩方案

Integrative test compression scheme based on symmetrical coding

应对大规模数字集成电路测试面临的日益严峻的挑战,在测试位重组基础上提出由游程赋值策略和对称编码组成的综合压缩方案。该赋值策略能够动态填充无关位,减少不必要的游程分裂,尽可能最大化游程长度。提出的对称编码受益于测试位重组和游程赋值所增加的长游程和端连续块,不仅提高码字的利用率,还能够用固定的4位短码字标识长达模式位数的端连续块,减少编码位数。给出的实验结果表明了所提综合压缩方案获得了较高的数据压缩率,远高于已发表的各类压缩方案,并且能够大量减少功耗。因而,该综合压缩方案具有较高的实用性,特别对于大规模集成电路测试,其效果更佳。

To cope with increasingly rigorous challenges that testing large scale digital integrated circuits confronts, a integrative compression scheme consisting of run-length filling strategy and symmetrical coding is proposed on the basis of test-bit rearrangement. The filling strategy can dynamically specify don＇t care bits to prevent run-lengths from unnecessary splitting and maximize the length of run-lengths. The proposed symmetrical coding benefits from long run-lengths and end-run blocks after the test-bit rearrangement and run-length filling, which not only heightens utilization ratio of code words, but also decreases their bit number through using four-bit code words to identify end-run blocks almost as long as the test pattern. The presented experiment results show that the proposed integrative scheme can obtain higher data compression ratios, which are much higher than those obtained using other compression schemes published up to now, and considerably decrease power dissipations. Hence the proposed integrative compression scheme has high practicability, and its effect is far better especially for testing large scale digital integrated circuits.