一种带有无效缓存路访问过滤机制的低功耗高速缓存

A Low Power Cache Architecture with Filtering Unnecessary Way Accesses

功耗是当今处理器设计领域的重要问题之一.随着多核处理器的普及,片上缓存占有了越来越多的芯片面积和功耗.提出一种带有无效缓存路访问过滤机制的低功耗高速缓存结构来降低CPU的动态功耗,具体为,通过无效缓存块的预先检查(Pre-Invalid Way Checking,PIWC)消除对无效缓存路的访问,及通过不匹配缓存路的预先检测(Pre-Mismatch Way Detecting,PMWD)消除对tag低位不匹配缓存路的访问.对实际程序的测试表明,65.2%-88.9%缓存路的无效访问可以通过以上方法被消除,约60.9%-85.6%由缓存访问带来的动态能耗从而被降低.同时,跟tag-data顺序访问方法相比,对于大多数程序,我们的方法可以获得5.1%-13.8%的节能效果提升.

Power has been a big issue in processor design for several years.As caches account for more and more CPU die area and power,in this paper,we propose a low power cache architecture with filtering unnecessary way accesses,which eliminates invalid way accesses by pre-invalid way checking（PIWC） and mismatch way accesses by pre-mismatch way detecting（PMWD） to reduce dynamic CPU power.Our evaluations show that,65.2%-88.9% unnecessary way accesses can be eliminated by PIWC and PMWD methods for real applications.And approximately 60.9%-85.6% energy caused by dynamic power of cache accesses can be reduced shown by our experimental results.Also,comparing to sequential tag-data access method,we can achieve 5.1%-13.8% improvement for most of the benchmarks.