应用于雷达系统的双路高速数据采集存储系统设计

High Speed Data Acquisition Storage System Design for Radar

介绍了一种用于对雷达回波I/Q信号进行双路高速采集与数据存储的系统,采样速率为200 MHz,分辨率为12位,存储深度为4 GB.该系统采用FPGA作为主控制器,ADS62P29作为高速数据转换器,K9K8G08U0M作为大容量数据存储器,通过USB实现系统与计算机之间的通信.利用Cadence软件和VHDL语言完成了系统设计、软件仿真及关键信号的完整性仿真.测试结果表明,ADC的有效位数可达10.69,输入信号为80 MHz的正弦信号时,两路ADC信号之间的相干系数达到0.998 4,可满足雷达系统对回波信号进行高精度相位测量的要求.

The paper introduces a high-speed data acquisition storage system with two channels applied to sampling the echo signals of radar receiver. The developed system can work at a sampling rate of 200 MHz with a 12-bit resolution and the 4 G bytes storage. The FPGA acts as the control core of the system, the ADS62P29 is used as the high - speed data converter, and the K9K8G08UOM is used as the large capacity da- ta storage. The communication between the system and the computer is through USB. The cadence and VHDL are used to complete the system design, software simulation and signal integrity simulation. Test re- suits show that the ADC ENOB is 10.69 and the synchronization between two channels are satisfied.