基于FPGA的高速ADC测试平台的设计

Design of High-speed ADC Test System Based on FPGA

高速ADC是超宽带宽通信、雷达信号处理等领域的关键组成部分,所以对它的测试越来越重要;针对传统测试系统成本高、难度大,利用FPGA和FFT算法设计了一套高速ADC动态参数测试系统;重点介绍了高速采样信号的降速处理、硬件电路以及FPGA的设计,从而完成对中科院微电子研究所自主研发的4G4bit高速ADC裸片的测试;最后通过对比测试结果和参考值验证了测试系统的可行性。

High speed ADC is the critical component in the Ultra-wideband communication systems, radar signal processing system ere, so the testing becomes more and more important. The traditional testing system for high-speed ADC is very difficult to be constructed and its cost is also very high. To overcome these shortcomings, this paper puts forward a kind of high speed ADC frequency domain char acteristics testing system based on FPGA and FFT algorithm. Focuses on slow down of high-speed signal , design the hardware circuit and FPGA, thus completing the independent research and development of the Institute of Mieroelectronics of Chinese Academy of Sciences 4G4bit high speed ADC bare chip test. Finallv. bv comDaring the test results and reference values verify the feasibility of the test system.