基于ACTEL反熔丝FPGA的分频器优化设计

Optimization Design of Frequency Divider Based on Actel Provided Anti-fuse FPGA

为了提高反熔丝FPGA芯片分频电路的系统工作频率,针对ACTEL公司提供的反熔丝芯片A32100DX,提出了基于计数器、移位寄存器与状态机的分频器VHDL编程方法,给出了硬件开发设计流程及3种设计方法的源程序,并对采用局部时钟及全局时钟、同步复位、异步复位、以及复位置零的计数器法在高低温环境下进行了后仿真对比分析,后仿真对比及烧写后的实测结果表明同步复位的移位寄存器分频方法后仿真速度最高,但在烧写后工作的可靠性不高,容易出现无输出现象,采用全局时钟且同步复位清零的计数器法速度较高,且工作可靠,已经在型号设计中采用。

To improve frequency divider of anti-fuse FPGA A32100DX provided by ACTEL Company, the counter, shift register and state machine based divider program methods with VHDL were presented. The hardware design flow and three divider source code were giv- en. The post simulation result of the divider with CLKBUFFER, QCLKBUFFER, synchronized reset, asynchronized reset and zero preset method show that shift register way has highest system frequency and unstable, while the counter with CLKBUFFER, synchronized reset and zero preset method can work well under real chip test.