分块渲染的三维图形中光栅操作的硬件实现

Hardware ROP implementation for tiled rendering 3D graphics

为了适应三维图形分块渲染的需要,使得像素经过渲染后能够快速的输出,文中给出了一种分块的光栅操作结构,各个块并行工作。每个并行模块均能实现渲染后片段的测试、混合、逻辑操作和屏蔽处理。该设计结构能够在一个时钟周期输出4个像素。设计进行了基于ModelSim的功能仿真并在Xilinx的FPGA上进行了综合实现,结果表明设计可行。

To meet the demand for tiled rendering 3D graphics, and to quickly output the ren- dered pixels, it proposed the architecture of tiled raster logic operation. The tile processors operate in parallel. Each processor implements fragment test, blending, logic operations and mask operations. The implementation is able to output four pixels each clock period. The design is simulated on ModelSim and implemented on Xilinx FPGA. The result shows that the design is workable.