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三维集成电路中硅通孔缺陷建模及自测试/修复方法研究 被引量：6

A 3D IC Self-test and Recovery Method Based on Through Silicon Via Defect Modeling
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摘要 硅通孔(Through Silicon Via,TSV)是3维集成电路(3D IC)进行垂直互连的关键技术,而绝缘层短路缺陷和凸点开路缺陷是TSV两种常见的失效形式。该文针对以上两种典型缺陷建立了TSV缺陷模型,研究了侧壁电阻及凸点电阻与TSV尺寸之间的关系,并提出了一种基于TSV缺陷电阻端电压的检测方法。同时,设计了一种可同时检测以上两种缺陷的自测试电路验证所提方法,该自测试电路还可以级联起来完成片内修复功能。通过分析面积开销可得,自测试/修复电路在3D IC中所占比例随CMOS/TSV工艺尺寸减小而减小,随TSV阵列规模增大而减小。 Through Silicon Via （TSV） is the key technology for vertical interconnections in 3D ICs, with insulator short and bump open being the two major types of TSV defects. In this paper, a TSV defect model is presented and the relationships between the linear oxide resistance/bump resistance and the TSV dimension are discussed. Based on the model, a method is proposed for detecting the voltage of the defects＇ resistance. To verify the proposed method, a self-test circuit which can detect both types of defects is designed, and it can be cascaded to achieve auto-recovery on chip. Then, the area overhead is analyzed and the results show that self-test/recovery circuits will occupy lower percentage of total chip area as CMOS/TSV fabrication technology scales down or as TSV array size increases.
作者 余乐 杨海钢 谢元禄 张甲 张春红 韦援丰
机构地区 中国科学院电子学研究所 中国科学院研究生院
出处 《电子与信息学报》 EI CSCD 北大核心 2012年第9期2247-2253,共7页 Journal of Electronics & Information Technology
基金 国家重大科学研究计划项目(2011CB933202)资助课题
关键词 3维集成电路 硅通孔 缺陷 自测试 扫描/修复链 3D IC Through Silicon Via （TSV） Defect Self-test Scan/recovery chain
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献15

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  • 4Zhang Jia, Yu Le, Yang Haigang, et al.. Self-test method and recovery mechanism for high frequency TSV array[C]. Proceedings of IEEE VLSI-SOC, Hong Kong, China, Oct. 3-5 2011: 260-265.
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同被引文献56

  • 1高德云,夏志东,雷永平,史耀武.BGA封装锡球制备技术研究[J].电子元件与材料,2005,24(10):56-60. 被引量：7
  • 2王伟,韩银和,胡瑜,李晓维,张佑生.SoC测试中低成本、低功耗的芯核包装方法[J].计算机辅助设计与图形学学报,2006,18(9):1397-1402. 被引量：4
  • 3Patti R S. Three-dimensional integrated circuits and the future of system-on chip designs[J].{H}PROCEEDINGS OF THE IEEE,2006,(6):1214-1224.
  • 4Beyne E,Swinnen B. 3D system integration technologies[A].Los Alamitos:IEEE Computer Society Press,2007.1-3.
  • 5Lu J Q. 3-D hyperintegration and packaging technologies for micro-nano systems[J].{H}PROCEEDINGS OF THE IEEE,2009,(1):18-30.
  • 6Lee H H S,Chakrabarty K. Test challenges for 3D integrated circuits[J].{H}IEEE Design & Test of Computers,2009,(5):26-35.
  • 7Lewis D L,Lee H S. A scanisland based design enabling prebond testability in die-stacked microprocessors[A].Los Alamitos:IEEE Computer Society Press,2007.1-8.
  • 8Zhao X,Lewis D L,Lee H H S. Pre-bond testable low-power clock tree design for 3D stacked ICs[A].Los Alamitos:IEEE Computer Society Press,2009.184-190.
  • 9Kim T Y,Kim T. Clock tree synthesis with pre-bond testability for 3D stacked IC designs[A].Los Alamitos:IEEE Computer Society Press,2010.723-728.
  • 10Buttrick M,Kundu S. On testing prebond dies with incomplete clock networks in a 3D IC using DLLs[A].Los Alamitos:IEEE Computer Society Press,2011.1-6.

引证文献6

二级引证文献18

电子与信息学报
2012年 第9期

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