期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology
原文传递
导出
摘要 A 10-bit 50-MS/s reference-free low power successive approximation register （SAR） analog-to-digital converter （ADC） is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC （CDAC） is implemented to cancel the offset of the latch-type sense amplifier （SA） to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit （FOM） of 61.1 fJ/conversion-step. A 10-bit 50-MS/s reference-free low power successive approximation register （SAR） analog-to-digital converter （ADC） is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC （CDAC） is implemented to cancel the offset of the latch-type sense amplifier （SA） to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit （FOM） of 61.1 fJ/conversion-step.
作者 乔宁 张国全 杨波 刘忠立 于芳
机构地区 Institute of Semiconductors Institute of Microelectronics
出处 《Journal of Semiconductors》 EI CAS CSCD 2012年第9期115-123,共9页 半导体学报（英文版）
关键词 successive approximation register analog-to-digital converter reference-free on-chip calibration energy efficient successive approximation register analog-to-digital converter reference-free on-chip calibration energy efficient
分类号 TN792 [电子电信—电路与系统] TP333 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献25

  • 1Huang Y C, Lee T C. A I 0-bit 100-MS/s 4.5-mW pipelined ADC with a time-sharing technique. IEEE Trans Circuits Syst 1: Reg Papers, 2011, 58(6): 1157.
  • 2Honda K, Furuta M, Kawahito S. A low-power low-voltage 10-bit 100-MSample/s pipeline A/D converter using capacitance coupling techniques. 1EEE J Solid-State Circuits, 2007, 42(4): 757.
  • 3Ryu S T, Song B S, Bacrania K. A 10-bit 50-MS/s pipelined ADC with opamp current reuse. IEEE J Solid-State Circuits, 2007, 42(3): 475.
  • 4Li J, Zeng X, Xie L, et al. A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications. IEEE J Solid-State Circuits, 2008, 43(2): 321.
  • 5Liu C C, Chang S J, Huang G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid-State Circuits, 2010, 45(4): 731.
  • 6Zhu Y, Chan C H, Chio U F, et al. A 10-bit 100-MS/s reference- free SAR ADC in 90 nm CMOS. IEEE J Solid-State Circuits, 2010, 45(6): 1111.
  • 7Yoshioka M, Ishikawa K, Takayama T, et al. A 10 b 50 MS/s 820 #W SAR ADC with on-chip digital calibration. IEEE ISSCC Dig Tech Papers, 2010:384.
  • 8Furuta M, Nozawa M, Itakura T. A 0.06 mm^2 8.9 b ENOB 40 MS/s pipelined SAR ADC in 65 nm CMOS. IEEE ISSCC Dig Tech Papers, 2010:382.
  • 9Liu C C, Chang S J, Huang G Y, et al. A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation. IEEE ISSCC Dig Tech Papers, 2010:386.
  • 10Verma N, Chandrakasan A P. A 25 #W 100 kS/s 12 b ADC for wireless micro-sensor applications. IEEE ISSCC Dig Tech Pa- pers, 2006:822.
Journal of Semiconductors
2012年 第9期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部