基于FPGA的高速以太网流量发生器

Implementation of High Speed Ethernet Traffic Generator Based on FPGA

采用高速以太网作为通信介质的高速传感器网络的开发过程中需要对节点的诸如自定义协议的正确性、吞吐能力、丢包率等指标进行测试.。用软件产生以太网流量存在精确性不足等问题,因此需要一款硬件平台产生可自由配置任意格式、长度、帧间隔、填充模式的高速以太网帧流量,以满足系统测试的需要。基于FPGA可以实现这样一个帧发生器,它与传统的逐层封包不同,创造性地采用了与数据并行置入的填充类型选择域作为配置数据,满足了灵活填充的要求。这样的结构具有高速性、灵活性和可扩展性,可全线速产生千兆或百兆以太网帧流量。

During the development of high speed sensor network in which high speed Ethernet is employed,it needs to carry out tests to figure out certain performance indexes like functional correctness,throughput capacity and packet loss.Thus it needs to build a hardware platform to generate Ethernet traffic of any frame formats,length,inter-frame gap and filling patterns.Such a traffic generator is implemented based on FPGA.As an innovation,frames are generated according to filling patterns works as configuration data that is parallel with the frame,instead of conventional way of encapsulation according to protocol levels.The architecture is highly flexible,scalable,and making full line speed 1 000 BASE or 100 BASE generation guaranteed.