H.264硬件解码核的FPGA实现

FPGA Implementation of H.264 Hardware Decoding Core

针对H.264/AVC的视频解码问题进行了研究,给出了H.264解码核的硬件实现方案,对熵解码CAVLC查表方案进行了优化。详细介绍了句法预测模块、反量化、逆DCT以及帧内预测模块的具体实现结构;并引入流水线、并行处理和状态机处理方法来提高处理速度,实现了解码结构上的优化。该算法在EP2S60F672C5ES FPGA上获得验证,结果表明给出的H.264解码算法是正确的,且有节省硬件资源和较快解码速度的优点。

Video decoding problem of H.264 is researched, Hardware implementation of H.264 decoder is given，and Look-up table scheme of entropy decoding CAVLC is optimized。In addition，the concrete realization structure of the syntactic module, the inverse quantization, the inverse DCT and intra prediction module are introduced in detail;And pipeline, parallel processing and state machine processing method are used to improve the processing speed and realize the optimization of decoding structure.The algorithm is tested and verified in EP2S60F672C5ES FPGA, the result shows that H.264 decoding algorithm is correct Which is presented and has the advantages of saving hardware resources and quicker decoding speed.