摘要
设计一种集抢答、定时、计时、违例、组号显示、声讯、自动复位的智能化竞赛设备。采用EDA技术进行了电路设计与仿真,硬件电路已在自主研发的FPGA创新开发实验箱上实现,技术性能达到了设计要求。
Design of an intelligent race equipment, it has preemptive answer, timing, unautlaonzed, group display, voice, and automatic reset function. Using EDA technology designs and simulates the circuit. The hardware circuit has already been realized by a FPGA innovative development experiment box which researched and developed by ourselves, design requirements. and the technical performance of the circuit can meet the
出处
《信息技术》
2012年第9期118-120,共3页
Information Technology
关键词
抢答器
电路设计
FPGA
仿真
preemptive answer
circuit design
FPGA
simulation
