SOC中嵌入式存储器阴影逻辑的可测性设计

DFT for the Shadow Logic of Embedded Memory in SOC

在使用ATPG工具对集成电路进行固定故障测试时,嵌入式存储器模块被视为简单的I/O模型,ATPG工具无法传递存储器周围组合逻辑的故障。通过研究SOC的可测性设计后,针对某数字信息安全芯片设计,利用扫描设计原理,改进了其存储器周围逻辑的设计,为阴影逻辑提供了可测试路径,提高了整个芯片的测试覆盖率和故障覆盖率。分析了设计的功耗、面积,确定了设计的有效性。

When the integrated circuits are tested by ATPG tools with the stuck-at model, the embedded memories inthe integrated circuits design are taken as simple I/O models, ATPG tools fail to transfer the faults of combinationallogics around the memories. Through the study of the DFT for SOC, the memory peripheral logics in a digitalinformation security chip design were modified with the scanning principle. The design provided detectable paths forthe shadow logics and improved the test coverage and fault coverage of the chip. The study analyzed the power andarea and verified the effectiveness of the design.