一种高速ZBT SRAM控制器设计

Design of a High-speed ZBT SRAM Controller

FPGA已经在雷达领域得到了广泛应用,然而其内部存储容量通常无法达到系统需求,因此必须为FPGA配置外部高速存储器。本设计采用两片高性能ZBT SRAM作为乒乓缓冲区交替工作,最高访问速率可达133MHz,使FPGA片外总存储容量达到32Mbit,满足设计要求。由于ZBT SRAM具有特殊的访问时序,必须使用FPGA的内部数字时钟管理模块DCM对时钟的相位进行精确控制,同时还要使用时序约束高级设计技术调整控制器的输入输出延时特性,使该控制器能够顺利地在FPGA内部信号处理系统和ZBT芯片之间完成高速数据交换。经过上述优化设计,采用VHDL代码编写可综合代码完成布线,目前该控制器已经成功地在某雷达导引头信号处理机中获得应用,验证了其有效性。

FPGA has been widely used in radar domains. However, FPGA internal memory storages are often insufficient for system requirement. Therefore external memory becomes necessary. In this paper, 2 high-performance ZBT SRAMs were chosen as Pingpong buffer for FPGA, maximum access frequency attains 133MHz. And the total storages achieve 32Mbits, which is adequate for designed aim. Because of ZBT SRAM＇ s special access timing, FPGA clock management modules have to be adopted to modify clock frequency and phase. Furthermore, to control FPGA I/O pad delay characteristic, advanced timing assignment tools were employed. So that de- signed ZBT SRAM controller can complete mass data exchanges between ZBT SRAM and FPGA internal module. Whole system was re- alized via synthesizable VHDL code, and implemented on Xilinx Virtex4 FPGA. Currently this design has been successfully used in cer- tain radar missile signal processor, indicating its validity was verified.