摘要
提出了带Cache和精确中断响应的CPU设计方案,实现指令集MIPS中选取15条指令作为本CPU的基本指令。采用基本5步流水线CPU设计,给出了指令Cache、数据Cache和精确中断响应的设计与实现。测试结果表明,该方案符合设计要求。
In this paper the design of CPU with Cache and precise interruption response was proposed.15 of the MIPS instruction set were selected as the basic instruction for the CPU.By using 5 stage pipeline,the instruction Cache,data Cache and precise interruption response were realized.The test results show that the scheme meets the design requirements.
出处
《实验室研究与探索》
CAS
北大核心
2012年第3期68-74,95,共8页
Research and Exploration In Laboratory
基金
国家自然科学基金项目(11001075)
河南省科技厅科技攻关项目(092102210327)
