基于FPGA/CPLD的7B8B编解码电路设计

Design of 7B8B Coding and Decoding Circuit Based on FPGA/CPLD

论述了一种基于FPGA/CPLD的7B8B编解码电路的设计和实现。根据光纤通信中mBnB码字通信的特点,设计了低累计不均值的7B8B编码表。用Verilog语言编写了编码电路和解码电路的代码,每个部分都生成了模块,进行了顶层文件和底层文件的整合,并对每个部分进行了仿真测试。编码电路由串并转换电路、锁存电路、数据编码电路、和并串转换电路组成,解码电路是编码电路的逆过程,也是由以上4个电路组成。最后验证和测试了编码电路和解码电路。仿真结果表明,整个设计符合对信号编解码的要求。

The design and implementation of a 7B8B coding and decoding circult based on FPGA/CPLD were expounded.According to the characteristics of mBnB symbol in optical fiber communication,the 7B8B coding table with low accumulation and no average value was dessigned.The codes of both coding and decoding circult were composed by using Verilog language,and a module was generated for each part.The top-lenel files and underlying files were integrated,and simulation test was performed in each part.The coding circuit is composed of the series circuit,the latch circuit,the data coding circuit,and string conversion circuit.Decoding circuit is the inverse process of the encoding circuit.The simulation results show that the design meets the requirements of signal encoding and decoding.