高速脉冲超宽带系统和芯片设计

System and chip design for high-speed impulse radio UWB

脉冲超宽带无线通信系统功耗低、复杂度低,但传输速率一般不高.本文提出高速脉冲超宽带无线通信系统方案,方案采用高速采样、低阶量化和数字处理技术,在保持较低的系统功耗和复杂度的条件下,实现了超过100 Mbps的脉冲超宽带无线信息传输.论文给出了系统方案、核心算法、芯片设计中的关键技术以及仿真结果.作为核心算法,提出的联合同步和信道估计算法具有低的复杂度,并易于实时实现.论文介绍了芯片设计中的数字基带芯片结构、接收机的状态转移和联合同步和信道估计算法的实现等关键技术.基于提出的方案,研制了数字基带芯片,其内核功耗小于100mW.采用研制的芯片,开发了试验系统,能够进行实时无线高清视频传输.对试验系统进行了实际测试,实测结果验证了该高速脉冲超宽带方案的有效性.

Impulse radio （IR） ultra-wideband （UWB） wireless communication system has the advantages of low power consumption and low complexity. However, its transmission rate is usually limited. This paper proposes a high-speed IR-UWB system scheme. By using high sampling rate, low resolution quantization, and digital processing, the proposed scheme achieves more than 100 Mbps wireless transmission rate with reasonable power consumption and complexity. The system scheme, core algorithms, key implementations in the chip design, and simulation results are given in the paper. As a core algorithm, a joint synchronization and channel estimation （JSCE） algorithm is proposed. The JSCE algorithm conducts synchronization and channel estimation at the same time. It has the advantage of low complexity and is feasible to real-time implementation. The implementation issues in the chip design, including the digital baseband chip structure, the state transform of the receiver, and the implementation of the JSCE algorithm are introduced. Based on the proposed system scheme, a digital baseband chip is designed and fabricated. The core power consumption of the chip is less than 100 mW. An experimental system is also implemented which uses the baseband chip as a core processor. The system is capable of real-time high definition video transmission. Experimental results on the experimental system validate the proposed system scheme.