增益恒定的数控振荡器设计

Design of Constant-Gain Digitally Controlled Oscillator

针对驱动能力可调的数控振荡器在输出频率范围内增益变化较大的问题,提出了一种电路设计方法,通过该方法设计出的数控振荡器结构具有增益恒定的特点。在SMIC 0.18μm logic 1P6M CMOS工艺下设计并实现了一个采用该振荡器结构的数控锁相环,数控振荡器的面积为0.025 mm2。实测数据表明,该数控振荡器输出的频率范围为76～208 MHz。当锁相环输出208 MHz高频时钟时,四分频后的峰峰值抖动为110 ps,均方根抖动为14.82 ps,数控振荡器的功耗为1.512 mW。

The gain of the driven-adjustable digitally controlled oscillator （DCO） varies largely in the output frequency range. To solve the problem, a circuit design method is presented to keep the DCO gain invariant in time-domain. To verify the proposed design method, a digitally controlled phase-locked loop （DCPLL） with the DCO is implemented by SMIC 0.18 Ixrn logic IP6M CMOS technology. The area of the DCO is 0.025 mm2. The measured results show that the frequency range of the DCO is from 76 M/-Iz to 208 MHz. When the frequency of the DCO is 208 MHz, the measured peak-to-peak jitter and cycle jitter of the corresponding four-divided clock are 110 ps and 14.82 ps, respectively. The corresponding power of the DCO is 1.512 mW.