全局自动图像配准算法加速器

Accelerator of the Global Automated Image Registration Algorithm

由于全局自动图像配准算法计算和存储复杂度高,不易实现实时处理,为此提出一种改进的基于块的全局自动图像配准算法加速器结构(BWAGIR II).该结构采用双组多体存储结构及优化的数据放置策略,支持在单个时钟周期内同时读取4×4插值窗口中的16个像素值;并采用定浮混合计算逻辑,以支持定点和浮点操作数的混合计算.FPGA实现结果表明,采用文中结构对5个BWAGIR II处理单元的数据吞吐率超过258×106像素?s.

Due to the high computing and memory requirements of the global automated image registration algorithm, an accelerator called BWAGIR II is proposed. It adopts a dedicated two-rank- multi-bank memory to support accessing 16 pixels within a 4 × 4 interpolating window in one cycle. And some logics are designed to support hybrid operations between a fixed-point operand and a floating-point operand directly. Experimental results from a FPGA-based implementation show that a throughput of over 258 ×10^6 pixels/s is achieved with 5 BWAGIR II units.