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一种轨至轨10位逐次逼近模数转换器的设计 被引量：2

Design of a Rail-to-Rail 10-Bit Successive Approximation A/D Converter
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摘要 设计了一款用于汽车电子MCU的轨至轨10位逐次逼近A/D转换器。采用单电容采样的DAC结构,保证A/D转换器的全摆幅输入范围。在后仿真验证中,采用频谱分析方法,标定寄生电容对DAC精度的影响,优化了版图结构。设计了片内低压差线性稳压器,提供稳定的电源电压信号。芯片采用GSMC 0.18μm 1P6M CMOS工艺实现。后仿真结果表明,在1.8V电源电压、51kHz输入信号频率、1MHz时钟频率下,无杂散动态范围(SFDR)为73.596dB,有效位数(ENOB)达到9.78位,整体功耗2.24mW,满足汽车电子MCU的应用需求。 A rail-to-rail 10-bit successive approximation A/D converter for automotive MCU was presented.In this circuit,DAC structure with single sampling capacitor was used to ensure rail-to-rail input amplitude of the ADC.In post-layout simulation,effect of parasitic capacitor on DAC accuracy was marked by spectrum analysis and the layout was optimized.On-chip LDO was designed to provide stable voltage source.The ADC was implemented in GSMC′s 0.18 μm 1P6M CMOS process.Post-layout simulation results showed that the A/D converter achieved an SFDR of 73.596 dB and an ENOB of 9.78 bit for 51 kHz input frequency and 1 MHz clock frequency.Operating at 1.8 V power supply,the circuit consumed a power of 2.24 mW,satisfying requirement of automotive MCU.
作者 陈铖颖 黑勇 胡晓宇
机构地区 中国科学院微电子研究所
出处 《微电子学》 CAS CSCD 北大核心 2012年第5期601-604,608,共5页 Microelectronics
基金 02国家重大科技专项"高可靠库单元与产品设计"(Y1GZ212001)
关键词 轨至轨 逐次逼近 A/D转换器 D/A转换器 Rail-to-rail Successive approximation Analog-to-digital converter Digital-to-analog converter
分类号 TN432 [电子电信—微电子学与固体电子学]
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参考文献6

  • 1CONG L, BLACK W C. A new charge redistribution D/A and A/D converter technique pseudo C2C ladder C] // Proc 43rd IEEE Midwest Symp Circ Syst. Lansing, MI, USA. 2000: 498-501.
  • 2PARK J], PARK HJ, K[M JW, et al. A 1 mW 10-bit 500 kS/s SAR A/D converter EC//IEEE Int Symp Circ Syst. Geneva, Switzerland. 2000: 581-584.
  • 3NEUBAUER H, DESEL T, HAUER H. A successive approximation A/D converter with 16 bit 200 kS/s in 0. 6 /lm CMOS using self calibration and low power techniques EC // 8th IEEE Int Conf Elec, Cire Syst. Malta. 2001: 859-862.
  • 4CONFALONLERI P, ZARNPROGNO M, GIRARDI F, et al. A 2. 7 mW 1 MS/s 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges EC3 //Proc 30th Euro Sol Sta Cite Conf. Leuven, Belgium. 2004: 255-258.
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同被引文献5

  • 1Huilong Xu, Zhiyong Zhar^, Runbo Sii, et al. Batch-fabricated high-performance graphene Hall elements [J].Nature Nanotechnol, 2013(1):487-498.
  • 2Jaejin Park, Ho-Jin Park, Jae-Whui Kim, et al. A 1mW 10-bit 500KSPS SAR A/D converter [C]// TheIEEE International Conference on Circuit and System,Geneva : IEEE,2000 : 581-584.
  • 3Confalonleri P,Zarnprogno M, Girardi, F,et al. A2.7mW lMSps 10b analog-to-digital converter withbuilt-in reference buffer and 1LSB accuracy program-mable input ranges [ C] //Solid-State Circuits Confer-ence, Proceeding of the 30th European. Leuven :IEEE, 2004 :255-258.
  • 4Neubauer H,Desel T,Hauer, H. A successive ap-proximation A/D converter with 16 bit 200 kS/s in 0. 6fj.m CMOS using self calibration and low power tech-niques[C]//The 8th IEEE International Conference onElectronics, Circuit and System. Malta: IEEE, 2001:859-862.
  • 5Razavi E Design of analog CMOS and integrated circuit[M]. New York: McGraw-Hill Company Inc, 2001.

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二级引证文献5

微电子学
2012年 第5期

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