摘要
提出了一种新颖的900～1 200MHz高线性低噪声放大器的拓扑结构,介绍了电路版图的设计方法。电路采用0.35μm SiGe BiCMOS工艺制作。测试结果显示,设计的高线性低噪声放大器增益为16.4dB,噪声系数为2.5dB,输入1dB压缩点为-6.0dBm,功耗为50mW(电源电压为5V),尺寸为720μm×950μm。
A new topology of low noise amplifier with high linearity was proposed, which operated from 900 MHz to 1 200 MHz. Method for layout design of the LNA was described. The circuit was fabricated in 0.35 μm SiGe BiCMOS technology. Test results showed that the LNA achieved a power gain of 16.4 dB, a noise figure of 2.5 dB and an ICP1 of -6.0 dBm, while consuming 50 mW of power from 5 V supply. The circuit occupied a chip area of 720 μm × 950 μm.
出处
《微电子学》
CAS
CSCD
北大核心
2012年第5期609-612,共4页
Microelectronics
