低电压低功耗宽带CMOS低噪声放大器的设计

Design of a Wideband Low-Voltage and Low-Power CMOS LNA

设计了一种应用于宽带(0.8～3.0GHz)接收机的低电压低功耗低噪声放大器。该放大器以折叠的共源共栅结构为基础,采用噪声抵消结构,通过两条并联的等增益支路来抵消匹配器件在输出端所产生的噪声,实现输入阻抗匹配和噪声优化。电路采用0.18μm CMOS工艺,利用Cadence软件进行设计和仿真。结果表明,该低噪声放大器在0.8～3.0GHz带宽范围内噪声系数(NF)小于3.2dB,电压增益(S21)在17.6～18.5dB之间,S11小于-12dB,S22小于-20dB,在0.8V电源电压下,功耗为9.7mW,版图面积为0.18mm2。

A wideband（0.8~3 GHz） CMOS LNA for low-voltage and low-power receiver was proposed based on folded cascode structure.Using noise cancellation technique,channel thermal noise and flicker noise of input MOSFET were canceled by paralleling two equal gain branches,to achieve lower noise figure and excellent wideband input matching.The circuit was designed in a 0.18 μm CMOS process and simulated with Cadence.Simulation results showed that the LNA achieved an operating frequency ranging from 0.8 GHz to 3.0 GHz with a noise figure less than 3.2 dB,a voltage gain between 17.6 dB and 18.5 dB,an input reflection less than-12 dB,and an output reflection less than-20 dB.The core LNA consumed 9.7 mW of power from a 0.8 V supply and it occupied an active area of only 0.18 mm2.