摘要
Verilog硬件描述语言用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模,并通过仿真软件完成硬件电路的调试,使得硬件开发周期和成本降低.介绍了Verilog HDL的特点和应用,并以自动售货机的设计为例,详细地说明了它的设计过程,并给出了代码,通过时序仿真波形证明设计的正确性.
Verilog Hardware description language is used for digital system modeling,including algorithm level and gate level as well as switch level.By debugging the hardware circuit,we can reduce hardware development cycle and cost.The paper introduces the features and application of Verilog HDL,and taking the design of vending machine as an example,illustrates in detail its design process,codes being given.The validity of the design is proved by timing simulation waveform.
出处
《陇东学院学报》
2012年第5期3-8,共6页
Journal of Longdong University