VHDL的语句常见错误分析

The Common Problems in Teaching VHDL

VHDL是硬件电路设计的首选语言之一,也是信息类专业重要讲授内容。本文结合VHDL的特点,分别阐述了在VHDL教学中遇到的常见问题,这些相关问题涉及到顺序与并发描述语句错用、信号和变量赋值的区分以及变量初始化的方法及时刻,对每个问题给出了具体的实例和正确的解决方法,并提出了今后教学中的改进。

VHDL is one of the top hardware circuit design languages,and is important in teaching information science.Based on the VHDL features,we describe common problems and their solutions in VHDL teaching.The problem in the teaching are the misusing sequential and concurrent statements,the assigning value of signal and variable,and the variable initialization approach.The improvement in future teaching is prosented.