期刊文献+

一种容忍老化的多米诺门 被引量:2

An aging tolerant domino gate
下载PDF
导出
摘要 负偏置温度不稳定性引起的晶体管老化已经成为影响集成电路可靠性的重要因素。高扇入多米诺或门是高性能集成电路中常用的动态电路,而负偏置温度不稳定性降低了多米诺或门的噪声容限并增大了其传输时延。本文提出了保持器和反相器均带有补偿晶体管的多米诺或门结构,通过开启补偿电路,使电路在老化以后仍然能够保持其抗干扰能力和传输延时,有效的延长了多米诺电路的使用寿命。 NBTI-induced transistor aging has become a prominent factor affetcing the reliability of circuits. Domino logic circuits are extensively app.lied in high-performance integrated circuits, but noise margin is decreased and transmission delay is'increased due to NBTI-induced circuit aging. A domino logic circuit with compensating keeper and inverter is proposed. The noise margin and the speed are maintained by opening the compensating circuit after domino logic circuit aged, so the lifetime is prolonged.
出处 《电路与系统学报》 CSCD 北大核心 2012年第5期91-97,103,共8页 Journal of Circuits and Systems
基金 国家自然科学基金资助项目(60876028 61106038 61274036) 博士点基金资助项目(200803590006 20110111120012)
关键词 多米诺电路 保持器 负偏置温度不稳定性 老化 补偿 Domino logic circuits keeper negative bias temperature instability aging compensation
  • 相关文献

参考文献15

  • 1W Jinhui, W Wuchen, G Na,H Ligang. Domino gate with modified voltage keeper [A]. Proceedings of Quality Electronic Design (ISQED), 2010 llth International Symposium on [C]. 2010.443-446.
  • 2V Kursun, E G Friedman. Domino logic with variable threshold voltage keeper [J]. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2003, 11(6): 1080-1093.
  • 3S A Tawfik, V Kursun. FinFET domino logic with independent gate keepers [J]. Microeleetronies Journal, 2009, 40(11): 1531-1540.
  • 4W Wenping, Y Shengqi, S Bhardwaj, R Vattikonda, S Vrudhula, F Liu, C Yu. The Impact of NBTI on the Performance of Combinational and Sequential Circuits [A]. Proceedings of Design Automation Conference [C]. 2007. DAC '07.44th ACM/IEEE, 2007. 364-369.
  • 5S Kothawade, K Chakraborty, S Roy. Analysis and mitigation of NBTI aging in register file: An end-to-end approach [A]. Proceedings of Quality Electronic Design (ISQED), 2011 12th International Symposium on [C]. 2011. 1-7.
  • 6M Agarwal, V Balakrishnan, A Bhuyan, K Kyunglok, B C Paul, W Wenping,'Y"B'o, C Yu, S Mitra. Optimized Circuit Failure Prediction for Aging: Practicality and Promise [A]. Proceedings of Test Conference, 2,00~.ITC 2008. IEEE International [C]. 2008. 1-10.
  • 7M Agarwal, B C Paul, Z Ming ,S Mitra. Circuit Failure Prediction and Its Application to Transistor Aging [A]. Proceedings of VLSI Test Symposium, 2007.25th IEEE [C]. 2007. 277-286.
  • 8R S Oliveira, J Semiao, I C Teixeira, M B Santos, J P Teixeira. On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications [A]. Proceedings of Test Workshop (LATW), 2011 12th Latin American [C]. 2011. 1-6.
  • 9C V Martins, J Semiao, J C Vazquez, V Champac, M Santos, I C Teixeira, J P Teixeira. Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors [A]. Proceedings of VLSI Test Symposium (VTS), 2011 IEEE 29th [C]. 20ll. 203-208.
  • 10Y Guihai, H Yinhe, L Xiaowei. A unified online Fault Detection scheme via checking of Stability Violation [A]. Proceedings of Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09. [C]. 2009.496-501.

同被引文献3

引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部