容错单片机的同步设计

Synchronization Design of FT - Single Chip Computer

文中阐述了容错单片机同步问题的设计思想及设计方法,特别强调了设计中的几个主要的技术关键,给出了三模冗余时钟的实验电路,并简单直观地分析了容错单片机的可靠性。

The treatise expounds a design theory & method about FT- single chip computer,especially emphasises the key points on synchronization technical design. It not only provides a test circuit of three modular redundant clocks,but also simply and directly analyses the reliability of FT- single chip computer.