期刊文献+

一种结构简单的低压、低功耗CMOS 4象限模拟乘法器设计 被引量:1

Design of a Compact Low-voltage,Low-cost CMOS Four-quadrant Analogue Multiplier
下载PDF
导出
摘要 提出了一种结构简单的低压、低功耗CMOS 4象限模拟乘法器,详细分析了电路的结构和设计原理.乘法器基于交叉耦合平方电路结构,并采用减法电路来实现.整个乘法器电路由8个MOS晶体管和2个电阻组成.基于SMIC 0.18μm CMOS工艺,采用Cadence Spectre软件对电路进行了仿真验证.仿真结果表明,在1.2 V单电源电压下,其输入电压线性范围约为±0.2 V,-3 dB带宽约为4.8 GHz,电路静态功耗低至25μW. A compact low-voltage, low-cost CMOS four-quadrant analog multiplier was presented and its basic configuration and design principle were analyzed. The proposed multiplier was designed based on a cross-coupled squarer topology and implemented with subtraction circuits. It consists of eight MOS transistors and two resistances. The circuit was simulated with Cadence Spectre based on Chartered 0.18 μm CMOS technology. The results indicate that the full-scale linear input range is ± 0.2 V and the simulated - 3 dB bandwidth is about 3 GHz for 1.2 V single power supply. The pow- er consumption of this analog multiplier is less than 25 μW.
出处 《南开大学学报(自然科学版)》 CAS CSCD 北大核心 2012年第4期63-66,共4页 Acta Scientiarum Naturalium Universitatis Nankaiensis
基金 天津市科技支撑计划国际科技合作项目(09ZCGHHZ00200)
关键词 模拟乘法器 低电压 低功耗 analog multiplier low-voltage low-cost
  • 相关文献

参考文献8

  • 1管慧.一种结构简单的低压CMOS四象限模拟乘法器[J].微电子学,1999,29(3):211-214. 被引量:5
  • 2Sawigun C, Mahattanakul J. A 1.5 V wide input range, high band-width, CMOS four-quadrant analog multiplier~ C ]//IEEE International Symposium on Circuits and Systems, May 18- 21,2008, Seattle, Washington. Piscataway: Institute of Electri- cal and Electronics Engineers, 2008:2 318 -2 321.
  • 3Naderi A, Khoei A, Hadidi K H. High speed low power four-quadrant CMOS current-mode muhiplier[ C ]//IEEE : Proceed- ings of the International Conference on Electronics, Circuits and Systems, December 11 -14, 2007, Marrakech, Morocco. Piscataway: Institute of Electrical and Electronics Engineers, 2007:1 308 -1 311.
  • 4Kumngern M, Dejhan K. Versatile dual-mode class-AB four quadrant analog multiplier[ J ]. Journal of Signal Processing, 2005, 2 : 1 304 -4 449.
  • 5Sawigun C, Demosthenous A. compact low-voltage CMOS four-quadrant analogue multiplier [ J ]. Electron Lett, 2006, 42: 1 149-1 150.
  • 6Liu W S, Liu S L. Design of a CMOS low-power and low-voltage four-quadrant analog multiplier[ J]. Analog Integrated Cir- cuits and Signal Processing, 2010, 63 (2) : 307 - 312.
  • 7Huang Z, Jiang M, Inoue Y. A highly linear and wide input range four-quadrant CMOS analog multiplier using active feed- back[J]. IEICE Transactions on Electronics, 2009, E92 -C(6) : 806 -814.
  • 8Razavi B. Design of Analog CMOS Integrated Circuits[ M ]. New York: Mac Graw-Hill, 2000.

二级参考文献4

  • 1Liu S I,IEEE Proc Circ Dev Syst,1996年,143卷,3期,174页
  • 2Liu S I,IEEE J Sol Sta Circ,1995年,30卷,9期,1025页
  • 3Liu S I,Int J Electronics,1995年,78卷,2期,327页
  • 4Liu S I,Electron Lett,1994年,30卷,25期,2125页

共引文献4

同被引文献6

引证文献1

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部