一种新的小时延故障模拟器

Novel fault simulator for small-delay faults

现有的小时延故障模拟方法一般采用基于故障注入的串行模拟方法,是一个显式的故障处理过程,在时间上还有很大的改善空间。通过深入研究小时延故障的传播特点,采用波形模拟和临界路径追踪相结合的方法,实现了对小时延故障的隐式处理,开发了一种新的小时延故障模拟器。以扇出源为研究点,通过向后追踪与向前分组传播相结合的方法实现整个模拟过程,并通过电路划分和临界路径的识别,减少了对无关故障的模拟消耗。新的模拟器在适用性和速度上都具有明显的优势,对ISCAS89电路的实验结果表明,与现有的小时延故障模拟器相比,模拟速度能提升1～2个数量级。

Existing small delay fault simulation methods generally adopt serial simulation method based on fault injection, which is an explicit fault processing and in terms of time there is still much room for improvement. This paper proposes a new simulation method for small-delay fault; through deeply studying the propagation feature of smalldelay fault, the method adopts the approach of combining waveform simulation and critical path tracing, and realizes the implicit processing of small-delay fault. Starting from fan-out stems, the simulation process is carried on with backward tracking and forward grouping. Through the identification of circuit partitioning and critical path tracing, the proposed method reduces the consumption on unrelated fault simulation. The experimental results on ISCAS89 circuit show that the proposed method has obvious advantages in terms of applicability and simulation speed; compared with the existing small-delay fault simulator, the simulation speed is increased by 1 - 2 orders of magnitude.