基于AMBA与WISHBONE的SoC总线桥KBar控制器的设计

AMBA and WISHBONE-based design of a SoC Bridge KBar bus controller

本文介绍了一种基于AMBA与WISHBONE的多总线SOC接口—KBar控制器的设计方案。本文提出了一种全新的SOC架构,并使用硬件描述语言实现了此架构中一个中枢系统SOC Bridge—KBar控制器(下文简称KBar)。KBar不仅实现了把SOC中的CPU与外围模块,片外Memory模块连接起来组成一个完整的SOC系统的功能,而且能成功实现对片外Memory(NOR FLASH和SDRAM)的访问。该控制器在Altera QuartusⅡ9.0下,利用CycloneⅢ EP3C25F324C8 FPGA成功综合,并得到了验证。

This article describes an AMBA Bus SOC with WISHBONE interfaces based-KBar controller design. Presented a new SOC architecture, and using hardware description language for the SOC Bridge-KBar a central system controller in this schema （hereinafter referred to as KBar）. KBar not only implements the CPU and peripheral modules in SOC, connecting external Memory module con- sisting of a complete SOC system function, but also outside the successful achievement of on-chip Memory （NOR FLASH and SDRAM） access. The controller in the Ahera QuartuslI 9, CyclonelI EP2C35F672C6 FPGA integrated successfully and has been veri- fied.