基于FPGA的实时图像中值滤波算法及实现

Real-image Median Filtering algorithm and Realization Based on FPGA

在数字图像处理中,传统中值滤波运算量大,特别是当滤波窗口变大时,运算量成倍增加,难以满足实时性要求。本文提出一种5×5窗口的快速中值滤波算法,易于使用现场可编程门阵列(FPGA)实现。相对于传统的算法,不但比较次数得到了大幅度的减少,而且利用FPGA并行处理的特点,处理速度也得到了提高。以分辨率为640×480的CMOS摄像头采集图像为实验对象,在硬件平台上验证算法的可行性,并且具有良好的滤波效果。

In digital image processing, the conventional median filtering can not meet the requirements of real-time, especially, when the filtering window is larger, the computational complexity increases more exponentially. In this paper, a kind of fast median filtering algorithm is proposed [or using FPC, A to implement. There was a greatly improved in the processing speed, compared with the con- ventional median filtering. The experimental results on filtering of 640 x 480 images show that the algorithm is viable in the hard- ware platform of FPGA.