基于FPGA的高阶大位宽超声相控阵滤波器设计

High orders and high bit-width FIR design for ultrasonic phased array system based on FPGA

超声无损检测中对不同应用采用不同频率特性的超声波换能器。超声相控阵无损检测系统的数字前端需要对不同中心频率的波束成型后的信号进行数字滤波,以便于后续的测量和成像。本文研制了大型超声相控阵无损检测系统中基于FPGA的高阶数、大位宽FIR滤波器,实现了单一滤波器硬件同时支持32位64项非对称系数和127项对称系数,样值位宽为24位,采样率为50MHz,工作频率为400MHz。

The ultrasonic transducers with different frequency characteristics are used for different applications in ultrasonic NDT （Non-Destructive Testing）. The heamformed signals must be processed by the FIR filter of ultrasonic phased array digital front-end for next stage measurement and imaging. This paper describes the design and implementation of the FIR on Xilinx Virtex-6 FPGA. The FIR supports 32-bit, 64 taps non-symmetrical coefficient set or 32-hit, 127 taps symmetrical coefficient set, and 24-bit sam- pling data at 50MHz sampling frequency in a single hardware. The working freouencv of the FIR is 400MHz.