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时间模式放大器设计

Design of time-mode amplifier
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摘要 互补性金属氧化物半导体(complementary metal-oxide semiconductor,CMOS)工艺尺寸的不断缩小从正面影响了系统的尺寸和性能,同时也对集成电路的可靠性和信号完整性产生了严重的负面影响。为了解决这个问题,提出了一种时间模式信号处理电路代替传统的电压模式信号处理电路,在此基础上,设计了一种基于BSIM3模型、0.18umCMOS工艺的时间模式放大器(TMA,Time-Mode Amplifier)电路,并对该电路进行了原理分析和Hspice仿真,实验结果表明,当输入时间差为皮秒级时,输出时间差会达到纳秒级,能很好地实现时间模式放大功能。 The continuous reduction of size in CMOS process impacts positively the size of the system and performance, and has an acute negative effect on the reliability of integrated circuits and signal integrity. To solve this problem, a time-mode signal processing circuit is introduced rather than traditional voltage-mode processing circuit. On the basis, a time-mode amplifier (TMA) circuit is proposed based on BSIM3 model and 0. 18urn CMOS process. The circuit is simulated by Hspice and its princi ple is analyzed. Simulation results show that: while the input time-difference variable is picoseconds, output time-difference variable is nanoseconds. The circuit can effectively realize the function of time-mode amplification.
出处 《计算机工程与设计》 CSCD 北大核心 2012年第11期4362-4365,4371,共5页 Computer Engineering and Design
基金 中央高校基本科研业务基金项目(531107040299) 国家自然科学基金项目(60876022) 湖南省自然科学基金项目(07JJ6132) 国家863高技术研究发展计划基金项目(2006AA04A104) 广东省产学研基金项目(2009B090300196)
关键词 互补性金属氧化物半导体 时间模式信号处理 时间模式放大器 时间差 HSPICE CMOS time-mode signal processing time-mode amplifier time-difference Hspice
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  • 1Lundstrom M S, Guo J. Nanoscale Transistors: Device Physics, Modeling and Simulation. New York: Springer- Verlag, 2006.
  • 2Chen M J, Huang H T, Huang K C, et al. Temperature dependent channel backscattering coefficients in nanoscale MOSFETs. In: IEDM Tech Dig, San Francisco, 2002. 39-42.
  • 3Taur Y, Warm C H, Frank D J. 25 nm CMOS design consid- erations. In: IEDM Tech Dig, San Francisco,1998. 789-792.
  • 4Lin H N, Chen H W, Ko C H, et al. The impact of uniaxial strain engineering on channel backscattering in nanoscale MOSFETs. In: Symposium on VLSI Technology, Kyoto, 2005. 174-175.
  • 5Liow T Y, Tan K M, Chin H C, et al. Carrier transport characteristics of sub-30 nm strained n-channel FinFETs featuring silicon-carbon source/drain regions and methods for further performance enhancement. In: IEDM Tech Dig, San Francisco, 2006. 199-202.
  • 6Barral V, Poiroux T, Vinet M, et al . Experimental determination of the channel backscattering coefficient on 10-70 nm-metal-gate, Double-Gate transistors. Solid State Electrons, 2007, 51(4): 537-542.
  • 7Cros A, Romanjek K, Fleury D, et al. Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling. In: IEDM Tech Dig, San Francisco, 2006. 399-402.
  • 8Shur M S. Low ballistic mobility in submicron HEMTs. IEEE Electron Device Lett, 2002, 23(9): 511-513.
  • 9Wang R S, Huang R, Kim D W, et al. New observations on the hot carrier and NBTI reliability of Silicon nanowire transistors. IEDM Tech Dig, Washington, 2007. 821-824.
  • 10Zhang L L, Wang R S, Zhuge J, et al. Impacts of non-negligible electron trapping/detrapping on the NBTI characteristics in Silicon nanowire transistors with TiN metal gates. In: IEDM Tech Dig, San Francisco, 2008. 123-126.

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