基于FPGA的高阶FIR抽取滤波器有效实现结构

An Efficient FPGA Implementation Structure of FIR Decimation Filter with High Orders

针对高阶FIR抽取滤波器直接型结构和多相滤波结构中存在乘法器资源使用较多,导致实际系统实现困难的问题,提出了一种适合FPGA实现的高效多相结构。该结构采用分时复用技术,通过提高FPGA工作时钟频率,对降采样后的滤波路数和每一路FIR滤波器中乘积和操作均复用一个乘法器,从而大幅节约了FPGA中乘法器资源的使用。结果表明,针对4 096阶滤波器和降采样率为512的实际抽取滤波器系统,只需要8个乘法器,且在Xilinx公司Virtex IV芯片上能稳定工作在204.8 MHz的时钟频率上。

For the implementation of the FIR decimation filter with higher orders,many multipliers are required if the traditional direct or poly phase structure is employed.This increases the implementation difficulty in many practical systems.In this paper,an improved poly phase structure of the decimation filter is designed,which is more suitable for FPGA implementation.In the proposed structure,multi-channels and operations on sum of products are realized with only one multiplier by increasing the clock frequency of the FPGA.In a practical decimation filter system with 4 096-order filter and 512-order decimation ratio,the proposed filter module stably works at a clock frequency of 204.8 MHz and only requires 8 multipliers.