一种基于多级流水线加法器的累加电路设计研究

Research on a Kind of Accumulator Basing on Multilevel Pipeline Adder

专用硬件电路常用来实现加速,以提升科学计算速度。在科学计算中,多个数据的累加是常见运算。在设计硬件累加器时,容易出现流水线阻塞问题。提出将数据依据流水线级次分成两类模块,不同类型的模块采用不同的累加方式。基于多级流水线加法器,在FPGA上实现了多个数据的累加。该设计消耗资源少,流水线利用率高,控制相对简单,尤其是在数据规模很大时,优势尤其明显。

Purpose-designed circuits can accelerate the speed of scientific calculation. Multiple data accumulation is a common operation in scientific calculation. It is easy to meet pipeline data hazards during designing the hardware accumula- tor. Our design is dividing those data into two kinds of modules according to pipeline level, and different modules using dif- ferent accumulation methods. Based on a multilevel pipeline adder, this design is implemented on a FPGA. It has less hard- ware resources and higher pipeline utilization, and the control is relatively simple. Especially for large-scale data, its advan- tages can be fully taken on.