线速路由器分组并行处理体系结构与性能分析

Parallel packet process architecture of line rate router and performance analysis

本文在分析路由器报文处理需求的基础上 ,探讨了报文多处理模块并行处理的体系结构 ,并以四个处理模块为例对分组处理时延做了定量分析和仿真。分析表明 ,当各模块处理能力总和与单处理模块结构处理能力相同时 ,多模块结构处理时延将大于单模块结构 ;当各模块处理能力总和大于单处理模块结构处理能力两倍时 ,系统处理的时延特性可得到明显改善 ,并且系统具有较好的可扩充性。

To implement high speed process and forwarding of packet in line rate router,this paper analyses the functional requirement of packet process in a router,then a parallel packet process architecture is discussed,and the numerical analysis and the simulation result are given Comparing with single process module architecture,the multiple process modules parallel architecture can reach higher performance,and has a good scalability