基于XeF_2硅刻蚀工艺的低阻硅衬底低损耗共面波导

Low-loss CPW Based on Low-resistance Si Substrate with XeF_2 Dry-etching Process

在低阻硅（1-10Ω.cm）衬底上采用XeF2硅腐蚀工艺成功制备了长度为2 mm、结构尺寸为w/s=40/60μm间断悬浮和全悬浮两种结构的共面波导。SEM照片显示器件释放后的悬浮结构未出现粘附或破裂现象。通过WYKO三维形貌观察得到两种结构共面波导悬浮信号线最大翘曲量分别为10μm和16μm。微波性能测试结果表明两种悬浮结构共面波导在1-10 GHz频率范围内插入损耗分别低于4.5 dB/2 mm和3.2 dB/2 mm,远小于制作在低阻硅衬底上的普通共面波导插入损耗9.4 dB/2 mm;在1-3 GHz频率范围内插入损耗分别低于0.54 dB/2 mm和0.17 dB/2 mm,小于制作在高阻硅（1 400-1 500Ω.cm）衬底上普通共面波导的插入损耗0.55 dB/2 mm。

The interval suspended CPW and full suspended CPW,based on low-resistance（1～10 Ω·cm） silicon substrate,were designed and fabricated with XeF2 dry-etching process.The SEM photography showed that the suspended structure of devices did not appear adhesion or rupture after releasing.The WKYO 3D shape morphology observation showed that the maximum warping amounts of interval suspended CPW and full suspended CPW were 10 μm and 16 μm,respectively.The insertion loss of interval suspended CPW and full suspended CPW was less than 4.5 dB/2 mm and 3.2 dB/2 mm at 1～10 GHz,which was superior to the insertion loss 9.4 dB/2 mm at 1～10 GHz of CPW fabricated on the same LR-Si substrate,and less than 0.54 dB/2 mm and 0.17 dB/2 mm at 1～3 GHz,which was still better than the insertion loss 0.55 dB/2 mm at 1～3 GHz of CPW fabricated on high-resistance（1 400～1 500 Ω·cm） substrate.