期刊文献+

基于二叉树的CVSL电路优化方法

CVSL circuit optimization method based on binary tree
下载PDF
导出
摘要 CVSL电路不同于互补CMOS逻辑那样具有固定的构成规则,对于复杂逻辑,若不对电路进行优化,则电路速度、版图面积、功耗等性能指标均会受到影响。因此用一种方法有规律的来完成CVSL电路结构的设计显得十分重要,传统的卡诺图化简法步骤过多,结构不够直观,针对这一缺陷,提出了用二叉树代替传统的卡诺图法的设计思路,从而使CVSL电路结构得到优化。分析结果表明,二叉树优化法较卡诺图法可使电路获得了更加高效的设计结果。 CVSL circuit is different from complementary CMOS logic that has a fixed composition rule. If the complex logic circuit is not optimized, the circuit speed, chip area, power consumption and other performance indicators will be affected. Therefore, a method which can regularly complete the CVSL circuit structure design is very haaportant. Since the traditional Kano figure simplifying method has some shortcomings (operation steps are too many, and structure is not intui- tive), a train of thought for the design is put forward in this paper, which adopts binary tree instead of the traditional Kano diagram method. The method makes CVSL circuit structure optimized. The analysis results show that the binary tree optimization method is better than Kano Tufake in the efficient circuit design.
出处 《现代电子技术》 2012年第22期174-176,共3页 Modern Electronics Technique
基金 国家"973"计划资助项目(2007CB714700) 国家自然科学基金资助项目(60776827)
关键词 电路结构优化 二叉树优化法 CVSL电路 互补CMOS逻辑 circuit structure optimization binary tree optimization method CVSL circuit complementary CMOS logic
  • 相关文献

参考文献14

  • 1朱正涌,张海洋,朱元红.半导体集成电路[M].2版.北京:清华大学出版社,2009.
  • 2RABAEY J M,CHANDRKASAN A.数字集成电路设计透视[M].2版.北京:清华大学出版社,2004.
  • 3康松默,王志功.CMOS数字集成电路:分析与设计[M].3版.北京:电子工业出版社,2009.
  • 4[美]威斯特,[美]哈里斯.CMOS超大规模集成电路设计[M].汪东,译.3版.北京:中国电力出版社,2006.
  • 5沈理.VLSI芯片的可测试性、可调试性、可制造性和可维护性设计[J].计算机工程与科学,2003,25(1):92-97. 被引量:6
  • 6WU Kang,BRADLEY R M.Theory of electromigrationfailure in polycrystalline metal films[J].Phys.Rev.B.50,1994(17):12468-12488.
  • 7PIERCE D G.Electromigration:a review[J].Microelec-tron Rellab.,1997,37(7):1053-1072.
  • 8GUTTMANN R J,CHAN K,GRAVES R J.Interconnecttechnology and design implications for future ASIC and sys-tem-on-a-chip(SOC)implementations[C]//Proceedings of1999IEEE/SEMI Advanced Semicoeluctos ManugactugingConfesence and Workshop.[S.l.]:IEEE,1999:164-167.
  • 9LIU Rui-chen,PAI C S,MARTINEZ E.Interconnect tech-nology trend for microelectronics[J].Solid-State Electro-nics,1999,43(6):1003-1009.
  • 10宋登元,宗晓萍,孙荣霞,王永青.集成电路铜互连线及相关问题的研究[J].半导体技术,2001,26(2):29-32. 被引量:20

二级参考文献54

  • 1[1]Special Issue: The 100-Millian-Transister IC[J]. IEEE Spectrum,1999,36(7):22-60.
  • 2[2]Special Issue: Nanometer Design and Test[J]. IEEE Computer,1999,32(11):42-74.
  • 3[3]Special Issue: System on a Chip[J]. IEEE Computer,1999,32(6):42-66.
  • 4[4]Special Issue: Technology 2000: Analysis & Forecast[J]. IEEE Spectrum, 2000,37(1):63-79.
  • 5[5]R Patel, K Yarlagadda. Testability Features of the Super SPARC Microprocessor[A]. ITC'93[C].1993.773-781.
  • 6[6]S Joshi,S Mitra, et al.Micro SPARC: A Case Study of Scan Based Debug[A]. ITC'94[C].1994.70-75.
  • 7[7]M Levitt,S Nori,S Narayanan, et al.Testability, Debuggability, and Manufacturability Features of the Ultra SPARC-I Microprocessor[A]. ITC'95[C].1995.157-166.
  • 8[8]H Hao, R Avra. Structure Design-for-Debug-The Super SPARC-II Methodology and Implementation[A]. ITC'95[C].1995.175-183.
  • 9[9]F Goshan. Test and On-Line Debug Capabilities of IEEE Std 1149.1 in Ultra SPARC-III Microprocessor[A]. ITC'00[C].2000.141-150.
  • 10[10]M Gallup, Wledbetter Jr,R McGarity,et al. Testability Features of the 68040[A]. ITC'90[C].1990.749-757.

共引文献31

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部