一种TLB结构优化方法

An Optimization Method of TLB Architecture

针对国产处理器地址代换旁路缓冲(TLB)性能不足的问题,通过对现有的虚实地址代换流程进行分析,提出设置独立第三级页表基址虚实映射缓存,对数据TLB结构进行优化的方法,减少低级页表虚实映射关系对高级页表虚实映射关系的挤占淘汰。SPEC CPU2000测试结果表明,近一半的课题能减少60%以上数据TLB的DM次数,少数课题甚至能减少90%以上,有效减少数据TLB缺失率。

Aiming at the problem of the inefficiency of the Translation Look-aside Buffer（TLB） of a homegrown microprocessor, based on the analysis of current virtual to real address mapping program, a method of TLB architecture optimization is put forward, which is to setup a separate virtual to real address mapping cache of the base address of third level page tables, decreasing the occurrence of replacement of higher level page table entries by lower levcl ones. After evaluation using SPEC CPU2000 benchmark, the Double Miss（DM） rate of the data TLB of almost half of the benchmarks is dropped down by 60% at least and some of the benchmarks are decreased by 90% above, such optimization can reduce data TLB miss rate effectively.